1. Field of the Invention
The present invention relates to manufacturing of integrated circuits on semiconductor substrates and, in particular, to a method of improving adhesion between an insulating layer and a cap layer within such integrated circuits.
2. Description of Related Art
In semiconductor fabrication processes, layers of insulating, conducting and semiconductor materials are commonly deposited and patterned to form integrated circuits (IC). These multilayer electronic components may further be provided with contact vias and line wirings formed in the insulating materials of such ICs, which, are referred to as interlevel dielectrics (ILDs). Typically, ILDs are made by damascene and dual damascene processing techniques.
In damascene processing, multilayer electronic components are made by depositing a dielectric material on a surface of a substrate to form an insulating layer and then patterning the insulating layer to form openings for trenches therein such insulating layer. Once trenches are formed, a conductive material is deposited into the trenches and then any excess conductive material may be removed from the structure surface to form damascene regions within the insulator layer.
Dual damascene processing similarly involves etching trenches within the insulating layer of the IC and further etching vias at the bottom of these trenches. In ICs where contact vias also extend downwardly from the bottom of the trenches, both the trenches and the downwardly extending vias are simultaneously filled with conductive material. This process forms both contact vias and integrated wires for interconnecting electrical devices and wiring at various levels within the IC.
Thus, in the process of forming multilayer electronic components, using both damascene and dual damascene processes, several layers are required to form the contact vias and integrated wires. For example, a typical multilayer electronic component may be built up from a first insulating layer on a substrate by forming an opening therein and then filling the opening with a conductive fill material to form conductive lines. However, prior to metallization, a barrier layer is typically provided within the openings in the first insulating layer to avoid metal diffusion between the conductive fill and the first insulating layer.
A second insulating layer is deposited over the first insulating layer and the metallization. Trenches and contact vias are then formed in this second insulating layer to form the line wirings and contact vias of the multilayer electronic component. Again, prior to metallization, a barrier layer may be deposited into the trenches and vias so as to coat the sidewalls of the openings in order to prevent any metal diffusion. The trenches and vias are then filled with metallization and the surface area of the substrate planarized, such as, by chemical mechanical polishing.
However, during the polishing process, the barrier layer may delaminate from the insulating layer resulting in interruption of polishing process as well as damage to the multilayer electronic component. This delamination problem is particularly severe in those devices having low k dielectric constant insulating layers. One method to decrease the problem of delamination between low k dielectric constant insulating layers and barrier layers has been to deposit a cap layer between the insulating layer and the barrier layer. However, the use of cap layers is ineffective as delamination occurs between the insulating and cap layers, and in particular, between low k dielectric constant insulating layers and cap layers.
Therefore, a need exists in the art for preventing delamination between insulating layers and cap layers, particularly, those insulating and cap layers used in single and dual damascene processes.